Optical networks use light signals to transmit data over a network. Although light signals are used to carry data, the light signals are typically converted into electrical signals in order to extract and process the data. The conversion of a light signal into an electrical signal is often achieved utilizing an optical receiver. An optical receiver converts the light signal received over an optical fiber into an electrical signal, amplifies the electrical signal, and converts the electrical signal into a digital data stream.
Burst-mode Passive Optical Networks (BPON) are widely used in the cable industry for transmission of light signals from an optical transmitter at a home to an optical module located at the hub/curb. The optical module typically includes an optical receiver. Typical optical light signals used in BPON applications can have a frequency of a 155 Mbps or greater. The use of burst-mode techniques requires fast and accurate handling of the incoming signals and accurate handling of the optical power levels both on the transmitter and the optical receiver sides. The optical receiver receives an incoming light signal in the form of a burst of upstream traffic from each user in a group of users. Each user is typically located at a different point in a network. Each incoming burst is typically a fixed size such as 500 bits. Due to attenuation, the strength or amplitude of each incoming burst can vary significantly depending on the user's distance from the optical receiver, the length of the optical fiber the incoming burst travels over, the strength of the transmitter that sends the incoming burst, etc. For example, after conversion into voltage, an incoming burst from one user might have an amplitude of 1 V, whereas another incoming burst from another user might have an amplitude of 1 mV. Each incoming burst includes a 8-bit preamble (10101010). In BPON systems, the 155 Mbps burst mode optical receiver must acquire a logic threshold of the incoming burst during this 8-bit preamble such that it can discriminate between a logic 1 and a logic 0. The logic threshold is the value used to discriminate between a logic 1 and a logic 0. The logic threshold is determined for each incoming burst. The optical receiver module then uses this logic threshold to slice the incoming signal and produce digital output.
FIG. 1 is a block diagram of a conventional optical receiver module 50 which includes a transimpedance amplifier 25, a logic threshold acquisition circuit (LTAC) 40, and a comparator 45. The transimpedance amplifier 25 is coupled to the LTAC 40 and to the comparator 45, and the LTAC 40 is coupled to the comparator 45.
An incoming burst impinges on a photodiode coupled to the transimpedance amplifier 25. The transimpedance amplifier 25 amplifies an input current signal generated by the photodiode into a relatively large amplitude output voltage (Vo) signal. The transimpedance amplifier 25 communicates this output voltage (Vo) signal to the LTAC 40 which generates a logic threshold (LT). The LTAC 40 communicates the logic threshold (LT) to the comparator 45. The comparator 45 can then be used to compare the logic threshold (LT) to the output voltage (Vo) signal from the transimpedance amplifier 25 to determine if the incoming burst is a logic 1 or a logic 0. For example, if the incoming burst is greater than the logic threshold, the incoming burst is construed as a logic 1, and if the incoming burst is less than the logic threshold, the incoming burst is construed as a logic 0.
FIG. 2 is a circuit diagram of a conventional LTAC 40 used in the optical receiver module 50 of FIG. 1. The logic threshold acquisition circuit 40 has a top or positive peak detector (PPD) circuit 14, a bottom or negative peak detector circuit (NPD) 16 and a resistor string 18.
The PPD circuit 14 generates a positive output voltage (Vop) responsive to the input signal (Vin). The NPD circuit 16 generates a negative output voltage (Von) responsive to the input signal (Vin). Thus, the PPD circuit 14 measures a maximum peak value and the NPD circuit 16 measures a minimum peak value of the incoming burst.
A resistor string 18 can be coupled in series between the outputs of the PPD circuit 14 and the NPD circuit 16. The maximum peak value (Vop) of the incoming burst is received at one end of the resistor string 18 and the minimum peak value (Von) of the incoming burst is received at the other end of the resistor string 18. An average value can be taken from the middle of the resistor string 18. This allows the average value (or arithmetic mean) of the maximum peak value (Vop) of the incoming burst and the minimum peak value (Von) of the incoming burst to be explicitly determined. This average value is the logic threshold that is used to discriminate between a logic 1 and a logic 0. The incoming burst is compared to the logic threshold such that when the incoming burst exceeds the logic threshold, the optical receiver module 50 assumes it is receiving a logic 1, and when the incoming burst is below the threshold, the optical receiver module 50 assumes it is receiving a logic 0.
In some BPON applications, there is a desire to provide an optical receiver module 50 which is designed for high speed and low power. For instance, in one implementation, the power supply of the optical receiver module 50 is 3 volts. The conventional LTAC 40 described above can be inadequate in these applications due to a lack of power supply headroom. In addition, the LTAC 40 needs to acquire the logic threshold with high precision. For instance, in one implementation, the LTAC 40 needs to acquire the logic threshold with 1 mV of maximum error in detecting the logic threshold. Unfortunately, in such low power implementations, the positive output voltage (Vop) and the negative output voltage (Von) are offset from each other by an arbitrary amount and do not have a predefined relationship. It can be difficult to accurately determine where the positive output voltage (Vop) and the negative output voltage (Von) are positioned with respect to the reference voltage (Vref).
FIG. 3 is a circuit diagram of a conventional positive peak detector (PPD) circuit 14 used in the LTAC 40 of FIG. 2. The PPD circuit 14 employs a capacitor 2, a resistor 4, a diode 6, a resistor 7, a reset switch 8, a buffer 10, and an amplifier 12. The resistor 4 is coupled between the capacitor 2 and a first node B. The diode 6 is coupled between node B and node C, and the switch 8 is coupled between the node B and the resistor 7 to ground. The buffer 10 is coupled between the node B and a node A, and the amplifier 12 is coupled between the node A and the diode 6 at node C.
The capacitor 2 is grounded. The buffer 10 generates the positive output voltage (Vop). The amplifier 12 receives the first output voltage (Vop) and an input voltage (Vnin). The amplifier 12 is a high gain amplifier having a gain A which can be between 100 and 1000. The amplifier 12 drives node B which is coupled to the diode 6.
Initially, node B is at ground potential due to closed switch 8. Before a new logic threshold acquisition begins, the reset switch 8 can be opened to remove the reset and discharge node B and the capacitor 2 to ground potential. The input voltage (Vin) is then applied. The diode 6 turns on in response to a positive voltage when the input voltage (Vin) is larger than the positive output voltage (Vop). If the input voltage (Vin) is smaller than the voltage (V1) at node B, then nothing happens and the positive output voltage (Vop) remains the same. If the input voltage (Vin) is larger than the voltage (V1) at node B, then positive output voltage (Vop) tracks or assumes the value of the input voltage (Vin). For example, when the input voltage (Vin) is larger than the voltage (V1) at node B, the difference between the input voltage (Vin) and V1 will be amplified by an amount approximately equal to the gain of the amplifier 12 and the diode 6 turns on which begins charging node B to a higher potential. The positive output voltage (Vop) follows the voltage (V1) at node B and is input to the amplifier 12. If the input voltage (Vin) begins to decrease, then the amplifer 12 reacts such that the output of the amplifier 12 decreases rapidly in proportion to the gain of the amplifer 12. Eventually this can cause the diode 6 to shut off. The voltage (V1) at node B is then “stored” at node B via the capacitor and no longer depends on the input voltage the input voltage (Vin).
It should be appreciated that a bottom peak detector 16 can be constructed by simply flipping the diode 6 so that the anode and cathode are reversed. This way, the diode 6 would turn on in response to a negative voltage when a input voltage (Vin) is smaller than a negative output voltage (Von). If the input voltage (Vin) is smaller than the voltage V1 at node B, then the negative output voltage (Von) tracks or assumes the value of the input voltage (Vin). If the input voltage (Vin) is larger than the voltage V1 at node B, then nothing happens and negative output voltage (Von) remains the same.
The differential signals (Vop) and (Von) are typically separated or offset from one another by an unknown voltage amount or offset. This makes it difficult to determine the logic threshold using the conventional LTAC which simply compares the positive output voltage (Vop) and the negative output voltage (Von) in an attempt to acquire the logic threshold. Due to the requirement for a large input signal range (1V), and due to voltage drops across the diode 6, inside the amplifier 12 and inside the unity gain buffer 10, such a peak detector could not be designed at Vcc=3.0V, while providing reasonable precision and offset performance.
Accordingly, it is desirable to provide high precision techniques for comparing a positive output voltage to a negative output voltage in the context of low power optical receiver modules. For example, it would be desirable to provide techniques which can eliminate the need to determine how much a positive output voltage signal is offset from a negative output voltage signals so that a logic threshold does not need to be explicitly determined. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.